Maxim MAX12557 User Manual download pdf (Page 12)

MAX12557

Dual, 65Msps, 14-Bit, IF/Baseband ADC

12 ______________________________________________________________________________________

PIN NAME FUNCTION

1, 4, 5, 9,

13, 14, 17

GND Converter Ground. Connect all ground pins and the exposed paddle (EP) together.

2 INAP Channel A Positive Analog Input

3 INAN Channel A Negative Analog Input

6 COMA Channel A Common-Mode Voltage I/O. Bypass COMA to GND with a 0.1µF capacitor.

7 REFAP

Channel A Positive Reference I/O. Channel A conversion range is ±2/3 x (V

REFAP

- V

REFAN

). Bypass

REFAP with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFAP

and REFAN. Place the 1µF REFAP-to-REFAN capacitor as close to the device as possible on the

same side of the PC board.

8 REFAN

Channel A Negative Reference I/O. Channel A conversion range is ±2/3 x (V

REFAP

- V

REFAN

). Bypass

REFAN with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFAP

and REFAN. Place the 1µF REFAP-to-REFAN capacitor as close to the device as possible on the

same side of the PC board.

10 REFBN

Channel B Negative Reference I/O. Channel B conversion range is ±2/3 x (V

REFBP

- V

REFBN

). Bypass

REFBN with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFBP

and REFBN. Place the 1µF REFBP-to-REFBN capacitor as close to the device as possible on the

same side of the PC board.

11 REFBP

Channel B Positive Reference I/O. Channel B conversion range is ±2/3 x (V

REFBP

- V

REFBN

). Bypass

REFBP with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFBP

and REFBN. Place the 1µF REFBP-to-REFBN capacitor as close to the device as possible on the

same side of the PC board.

12 COMB Channel A Common-Mode Voltage I/O. Bypass COMB to GND with a 0.1µF capacitor.

15 INBN Channel B Negative Analog Input

16 INBP Channel B Positive Analog Input

DIFFCLK/

SECLK

Differential/Single-Ended Input Clock Drive. This input selects between single-ended or differential clock

input drives.

DIFFCLK/SECLK = GND: Selects single-ended clock input drive.

DIFFCLK/SECLK = OV

: Selects differential clock input drive.

19 CLKN

Negative Clock Input. In differential clock input mode (DIFFCLK/SECLK = OV

), connect a differential

clock signal between CLKP and CLKN. In single-ended clock mode (DIFFCLK/SECLK = GND), apply

the clock signal to CLKP and connect CLKN to GND.

20 CLKP

Positive Clock Input. In differential clock input mode (DIFFCLK/SECLK = OV

), connect a differential

clock signal between CLKP and CLKN. In single-ended clock mode (DIFFCLK/SECLK = GND), apply

the single-ended clock signal to CLKP and connect CLKN to GND.

21 DIV2 Divide-by-Two Clock-Divider Digital Control Input. See Table 2 for details.

22 DIV4 Divide-by-Four Clock-Divider Digital Control Input. See Table 2 for details.

23–26, 61,

62, 63

Analog Power Input. Connect V

to a 3.15V to 3.60V power supply. Bypass V

to GND with a parallel

capacitor combination of ≥10µF and 0.1µF. Connect all V

pins to the same potential.

27, 43, 60

Output-Driver Power Input. Connect OV

to a 1.7V to V

power supply. Bypass OV

to GND with a

parallel capacitor combination of ≥10µF and 0.1µF.

Pin Description

1 2 ... 7 8 9 10 11 12 13 14 15 16 17 ... 27 28

MAX12557 1

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Maxim MAX12557 User Manual Page 12

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